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as91l1002 july 2004 jtag test sequencer description the as91 l10 02 devi c e p r o v ides a sol u tion to perform st and al one i eee1149.1 tests with out any third pa rty test hard w a r e. the d e vice e x ecute s te sts that have be en transl a ted fro m the s e rial vector fo rm at (svf) to the com p a c t binary format, bvi which is store d in a flash mem o ry. upon com p letion of th e test ru n the us er is presented with pass/fail i n formation, thus e nablin g a high d e g r ee of confide n ce i n the operation of the pcb. the as91l 1 002 can b e controlled by usin g on e of two differen t sou r ces: a power-on reset ci rcuit or a front pa nel switch. a n y one of these can ca use the as9 1 l100 2 to exe c ute te sts that have be en lo aded in to the fla s h memo ry. whe n the a s 91l10 02 i s runni ng and perfo rming the test s, sta t us lin es are fed off chip to en able the use r to hold the pcb in a safe state until compl e tion of the tests. whe n the t e sts have completed, th e status of the executio n is pre s e n te d off chip through a s t atus line to indicate the pass/fail condition. key features perform s ieee1149.1 test s in stand alo ne mode without any 3 rd party test hard w a r e eliminates th e need fo r firmware d e ve lopment, thereby spee ding up time to market as91l10 02 can be used t o perfo rm sel f tests on multiple pcb s on a sy ste m in parall e l pinout and feature set compatible (complete se con d so urce) with the fi recron jts02 device available in a 100 -pin lqfp o r a 100 -pi n fpbga lead free pa ckag e device block diagram tm s pa ra ll e l t o s e ri al c o nv er si o n td o pa ra ll e l t o s e ri al c o nv er si o n t d i s e ri al t o pa ra l l e l co nve r s i on t c k con t ro l l ogi c co nt ai n i ng 16 b i t r t i c oun t e r s m o d e co ntr o l regi s t ers flash interfac e logi c add r es s a nd data ieee 1149.1 interfac e log ic lf sr signature com p act o r p o w e r on re set r o r as91l 10 02 ru n sw i t c h bvf execution state mac h ines as91 l10 02 r unn i ng f l ag as91l1 002 pass/f a i l flag ieee1149 . 1 in t e r f ac e p o r t figure 1 - as91l10 02 jt ag te st seq u encer alliance semiconductor 2575 augusti ne dr i v e ? santa clara, ca 95054 ? t: 40 8-855-4900 ? f: 408-855-49 99 ? w w w . a ls c.com
july 2004 as91l1002 bist sequencer power on operation t e st pa ss /fa i l pc b as se r t s s i gn al t o re se t as9 1l 10 02 (l ow). s i gn al jt s 0 2 _ r s t bi st s e q u e n c e r devi ce resets ass e r t s a s 9 1l 10 02 _r s t _ o ut (l ow) bi s t st at u s bi t s (0 & 1 ) status (0) (low) b u s y /i d l e status (1) (low) p a s s /fail p c b d e - a s s e r ts si gn al t o r e s e t as 91 l1 00 2 ( h i g h ) s i gn al as 9 1l1 00 2 _r st bi st s e q u e n c e r d e vic e e x i t s re set deasserts a s 9 1l 10 02 _r s t _ o ut (h ig h) asser t s as 91 l1 00 2 _ r un _o ut (h ig h) bi s t s t at us bi ts (0 & 1 ) st at u s ( 0 ) (h ig h) bu sy i d le status (1) (low) p a s s /fail b i st se q u e n c e r d e v i ce wa its 15 0u s for bist f l as h t o b e c o m e av ai lab l e b i st se q u e n c e r d e v i ce a c ce s s e s bi st f l a s h an d s t a r t s i e e e 1 1 4 9 . 1 s t ored te st s b i s t s e que nc er s t or ed pr og ra m m a b le d e la y pri o r to ie ee 1 149 .1 b u s ac ce ss bi st se qu e n c e r lo ad & ru n iee e 11 49 . 1 tes t gen e rate c r c , st ore & c o mp are e n d of st o r e d te st s bi s t s e q u e n c e r b i s t st at u s b i ts ( 0 & 1 ) st atu s (0) (h ig h) bu sy / i d l e st atu s (1) (h ig h) pa ss / f ail b i s t s e que nc e r de - a ss er t s as 91 l1 00 8 _ r u n_out (low) bi st st a t us b i t s ( 0 & 1) s t at us (0 ) ( l o w ) b u s y / i d l e pc b re ac t s t o as 91l1 00 2 i / o a n d or bist s t at us bit s bo ar d c o n t in ue s t o b o o t fa i l pa ss no yes figure 2 - as91l10 02 po w e r on seq u ence the as91 l 1002 doe s not requi re a microprocessor to o perate and run ieee1149.1 tests. it can be used to p e rform di agn ostics on the p c b . i n sy st ems wit h mul t iple ca rd s, al l car d s ca n simultan eou sl y execute self tests witho u t pro c e s sor i n tervention, thereby significantl y reducing test time. as91l1002 utilizes ieee1149.1 tests gen erat ed by i ndu stry stand ard a t pg tool s, thereby elimi nating the n eed fo r cust om firm ware developm ent resulting in fa ster time to m a rket. in the as91l1002, the i eee1149.1 t e st prep aration i s a two - ste p p r ocess. th e first step i s to co nvert th e indu stry st anda rd svf format into the compa c t alliance bin a ry bvf file. o ne o r m o re ieee1149.1 tests re pres ented a s alliance bvf files can the n be fu rther com p re ssed into a n alliance bvi f ile whi c h i s th en expo rted t o a bin a ry file for prog ramming into the flash device, and then used by the as91l10 02 for test ex ecutio n. the u s e r is able to spe c i f y the tck rate for ea ch ind i vidual test executio n ba sed o n a prog ram m abl e divider wi thin the as91l1 002, along with a prog ram m abl e test start d e lay time based up on the numb e r of tcks. these fe atures ena ble mu ltiple test s to be store d , in the as91l10 02 t e st flash. it allows ea ch test to opera t e at different tck rate, and allows for sufficient settling time before ea ch t e st sta r ts to en sure th at the pcb i s in a stable co ndition. www .a lsc.com alliance semiconductor 2 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1002 signal descriptio n pin name pin num be r lqfp pin num be r fpbg a description toe 88 b6 test outp ut enable: wh e n this sig nal i s take n to logic ?0?, all i/o on the devi c e is pl aced i n highz. por 14 f4 powe r on re set: this sign al whe n take n to logic ?0? cau s e s the as91l100 2 to reset. whe n the sign al retu rn s to logic ?1? the as91l10 02 starts test executio n. sw_run 10 e3 switch as91 l100 2 ru n: this si gnal wh en take n to logic ?0? ca use s the as9 1l10 02 to re set. when the sign al ret u rn s to logic ? 1 ? the as91l 1002 starts test executio n. osc_i n 16 f1 oscillator input: prov ides the master cl ock into the as91l10 02, max freq 66 mhz. busy_idle 25 k1 busy idle: this outp u t indicate s the st ate of the as91l10 02. whe n hig h , it indicate s tha t the as91l10 02 i s active. pass_fail 24 j 1 pass fail: this output provides s t atus of the tes t executio n. when at logi c?1? after test execution the store d ieee1149.1 test ha s failed du e to data er rors . flash_a dd[0..23] 70, 69, 67, 65 , 64, 63, ,61, 60, 57, 28, 29 , 30, 31, 32, 35 , 36, 37, 40, 41 , 42, 45, 46, 47 , 48 d10, d9, e8, e10, e9, f7, f10, f9, g10, j 2 , k3, j 3 , h4, j4, h5, j 5 , k5, k6, j 6 , h6, j 7 , h7, j8, k8 flash add: these output s provid e the address pins to the fla s h devi c e tha t is used to st ore the ieee1149.1 tests. flash_ d b[0 ..15] 72, 75, 76, 78 , 79, 80, 81, 83 , 84, 85, 92, 93 , 94, 96, 97, 98 c9, c1 0, b10, a9, a8, b8, a7, b7, c7, c6, c5, c4, b4, a4, b3, a3 flash db: t hese input s p r ovide the sto r ed ieee1149.1 test data withi n the flash de vice to the as91l10 02 seque ncer. flash_rd 50 k10 flash rea d : this ou tpu t provides a n active ?0? sign al to indicate that the as91l10 02 wi she s to read d a ta fro m the flash d e vice. trst 22 h2 trst: this o u tput sign al p r ovide s the ieee1149.1 trst si gnal f o r the device s to be tested . tms 21 g2 tms: this output signal provides the ieee1149.1 tms signal fo r the device s to be tested. tck 87 a6 tck: this o u tput sign al pro v ides the ieee1149.1 tck sig nal fo r the device s to be tested. the clo c k freque ncy is based up on the frequ en cy of oscillator to the as91l1 00 2 and is p r og rammabl e for each test s execution. www .a lsc.com alliance semiconductor 4 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1002 pin name pin num be r lqfp pin num be r fpbg a description tdo 20 g1 tdo: thi s output signal provides the ieee1149.1 data for the d e vice s to be tested. it shou ld be con n e c ted to the tdi pin o n the first dev ice in the ieee1149.1 chain. tdi 19 g3 tdi: this input signal receives the ieee1149.1 data from the device s to be tested. it should be con n e c ted to the tdo pi n on the last de vice in the ieee1149.1 chain. device_tck 62 f8 silicon tap port signal device_t di 4 a1 silicon tap port signal device_tdo 73 a10 silicon tap port signal device_tms 15 f3 silicon tap port signal signal groun d 55,56, 89, 38, 86, 11, 26, 43 , 59, 74, 95, 2, 17, 90 j 9 ,g9,b5, d6, g5, c3, d7, e5, f6, g4,h8, a5, f2, b1 3.3 v supply 39, 91,23, 3, 18, 34, 51, 66 , 82,54 h9, c8, d4, e6, f5, g7, h3, h1, d5, g6 table 1 - signal desc ripti on www .a lsc.com alliance semiconductor 5 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1002 signal functions signal name signal function trst trst: this o u tput sign al p r ovide s t he ieee1149.1 trst signal for the device s to be tested. toe test outp ut enable: wh e n this sig nal i s take n to log i c ?0? all i/o on the device i s placed in hig h z. tms tms: this output signal provides t he ieee1149.1 tm s signal for the devices to be tested. tdo tdo: thi s output signal provides the ieee1149.1 dat a for the devices to be test ed. it sho u ld be co nne cted to the tdi pin on t he first device in the ieee1149.1 chai n. tdi tdi: this input signal rece ives the ieee1149.1 data from the devi c es to be tested. it sho u ld be co nne cted to the tdo pi n on t he last device in the ieee1149.1 chai n. tck tck: this o u tput sign al pro v ides t he ieee1149.1 t c k signal for the device s to be tested. the cl ock frequency is based up on the frequency of oscillat o r to the as91l10 02 a nd is prog ram m able for e a ch tests exe c u t ion. sw_run switch as91 l100 2 ru n: this si gnal wh en take n to logic ?0? cau s e s the as91l10 02 to reset. whe n the sig nal retu rns to logi c ?1? the as91l10 02 start s test executio n. rst_out reset out: this output signal pul ses low before the start of each test execution. it is us ed to reset the flas h devic e to ens u re that they are in a stable sta t e before the as91l10 02 a c cess the sto r ed data. por powe r on re set: this sign al whe n take n to logic ?0? causes the as 91l1 002 to reset. whe n the sig nal retu rn s to logic ?1 ? the a s 91l10 02 st arts te st execution. pass_fail pass fail: this output provides s t atus of the tes t exec ution. when at logic ? 1? af ter test executio n, the store d ieee1149.1 test ha s failed due to data e rro rs. osc_i n oscillator inp u t: provides the maste r cl o ck into the a s 91l10 02, m a x freq 66 m h z. flash_rd flash rea d : this output provides an ac tive ?0? s i gnal to indic a te that the as91l10 02 wishe s to rea d data from the flash d e vice. flash_db[0..15] flash db: t hese input s provide t he stored ieee1149.1 test data within the flash. flash_a dd[0..23] flash add: these output s provid e t he address pin s to the flash d e vice that is u s ed to store the i eee1149.1 tests. busy_idle busy idle: this outp u t indicate s the st ate of the as91l1 002. wh en hig h , it indicate s the as91l10 02 is a c tive. table 2 - signal function s www .a lsc.com alliance semiconductor 6 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1002 absolute maximum ratings parameter maximum range supply voltage (vcc) -0.3v to 5.5v dc inp u t voltage (vi) -0.5v to vcc +0.5v max sink cu rrent whe n vi = -0.5v -20ma max sou r ce current wh en vi = vcc + 0. 5v +20ma max jun c tion tempe r ature with power a pplied tj +12 5 deg ree s c max storage temperature -55 to +150 d egre e c table 3 - ab solute ma ximum rating s note: str ess abov e the stated maximu m v a lues ma y cause irreparable dam a ge to the d e v i ce, correc t oper a tion of the dev i ce at these v a lues is not guar a nte e d. recommended operating conditions parameter opera t ing range supply voltage (vcc) 3.0v to 3.6v input voltage (vi) 0v to vcc output voltag e (vo) 0v to vcc operating te mperature (t a) comm ercial 0 c to 70 c industri a l (ta ) -40 de g c to +85 d eg c, 3. 00v to 3.6v table 4 - re commended opera t ing conditions dc electrical characteristics sy mbol parameter min max conditio n v ih minimum hi g h input voltage 2.0 5.25 v il maximum lo w input voltage -0.3v 0.8v sy mbol parameter value conditio n v oh minimum hi gh output voltage 2.4v ioh=2 4 ma or 8ma as defined by pi n v ol minimum lo w output voltage 0.4v iol=24ma o r 8ma as defined by pi n i oz tris tate output leak age -10 o r 10 ma www .a lsc.com alliance semiconductor 7 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1002 sy mbol parameter min max conditio n i cc maximum qui escent s u pp ly c u rr ent 2ma i ccd maximum dynamic s u pp ly c u rr ent 80ma tck freq e q u a l to 10 mhz table 5 - as 91l10 02 dc electrical ch arac teris t ics packaging information the as91l1 0 02 is availa ble in a 100-pin lqfp or a 1 00-pi n fpbg a lead free p a ckag e. d1 sq u a r e 1 d s qua r e 3 d 1 ba si c 14 . 0 0 d ba si c 18 . 0 0 l 0. 15 0. 6 0 a 2 m i n no m m a x 1 . 35 1 . 40 1. 4 5 l1 re f 1. 0 0 a ma x . 1. 6 0 b mi n m a x 0 . 1 7 0 . 2 7 a 1 0. 0 5 0 . 15 e ba si c 0. 5 0 j e d e c re f # ms - 0 2 6 cc c ma x 0. 0 8 dd d no m 0. 0 8 sym b o l 100 le a d to l . le a d s mi n m a x not e s : 1 . a l l l i n e a r d i m e n s io n s a r e i n m i l l i m e t e r s . 2 . pl as t i c bo dy d i m e n s i o ns do n o t i n c l u d e f l as h o r pr o t usi o n . m ax al l o w a bl e 0 . 2 5 per si de. 3 . l ead c o un t o n d r a w i n g n o t re presentat i ve o f a c tual packag e. 3. m a 0.2 5 0 . 09/0.20 t y p 0 - 7 typ l l1 b a1 - c - cc c l e ad co pl a n a r i t y al a l al a- b s d s a2 a 12 n o m 12 n o m e figure 4 - l q fp-1 00 www .a lsc.com alliance semiconductor 8 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1002 revisions r e v . d e s c r i p t i o n e c n d a t e a initial document release. 91253 12-04- 01 b updated ball cop l anarit y limits from 0.20mm to 0.15 mm. d e a b 2 c 0.15 c d1 e1 c d g h i k 1 2 3 4 5 6 7 8 9 1 0 f e b a b 0 . 2 5 m c 0 . 2 5 m c a b dimensions s y mb o l m i n . n o m . m a x . a - - - - 1 . 7 0 a 1 0 . 3 0 - - - - a 2 0 . 2 5 - - 1 . 1 0 b 0 . 5 0 0 . 6 0 0 . 7 0 d 1 1 . 0 0 b s c d 1 9 . 0 0 b s c e 1 1 . 0 0 b s c e 1 9 . 0 0 b s c e 1 . 0 0 packag e num ber fbg a 010 0-11 f jedec ref # mo-19 2 var. a a c-1 figure 5 - fp bg a-1 00 www .a lsc.com alliance semiconductor 9 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1002 device selector g u ide and ordering information as91l x xxx u u - cc pp - temp - l al i a n c e s emi c ond uc t o r syste m so lu tio n d e vice fa mily 1001 1002 1003 1006 pro duc t v e rs i o n s = s t andar d u = 16 - b it use r cod e bu = 8- bi t s t at us / u s e r c ode e = e nhanc ed c = com mer c i al (0 t o 70 d egrees c) i = i ndus t r i a l (- 40 t o 85 deg rees c) pa cka ge l 100 = 10 0 pi n lqf p f 100 = 1 00 pi n f p bga c l o ck spe e d 10 = 10 m h z tck 40 = 40 m h z tck b l ank = le aded f = l ead f r ee g = green figure 6 - pa rt numb erin g guide www .a lsc.com alliance semiconductor 10 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1002 part number des c ription as91l10 02s ? 10l10 0-c jtag te st seque ncer, 10 0-pin l q fp packa ge, co mmercial as91l10 02s ? 10l10 0-cf jtag te st seque ncer, 10 0-pin l q fp packa ge, co mmercial, lea d free as91l10 02s ? 10l10 0-i jtag te st seque ncer, 10 0-pin l q fp packa ge, ind u strial as91l10 02s ? 10l10 0-if jtag te st seque ncer, 10 0-pin l q fp packa ge, ind u strial, lea d free as91l10 02s ? 10f100 -c jtag te st seque ncer 10 0 - pin fpbga packa ge, co mmercial as91l10 02s ? 10f100 -cg jtag te st seque ncer 10 0 - pin fpbga, comm ercial, gree n pa ckag e as91l10 02s ? 10f100 -i jtag te st seque ncer 10 0 - pin fpbga packa ge, ind u strial as91l10 02s ? 10f100 -ig jtag te st seque ncer 10 0 - pin fpbga, indu strial, gre en pa ckage as91l10 02s ? 40l10 0-cf jtag te st seque ncer, 10 0-pin l q fp packa ge, co mmercial, lea d free, 40 mhz tck as91l10 02s ? 40l10 0-if jtag te st seque ncer, 10 0-pin l q fp packa ge, ind u strial, lea d free, 40 mhz tck as91l10 02s ? 40f100 -cg jtag te st seque ncer 10 0 - pin fpbga, comm ercial, gree n pa ckag e, 40 mhz tck as91l10 02s ? 40f100 -ig jtag te st seque ncer 10 0 - pin fpbga, indu strial, gre en pa ckage, 40 mhz tck table 6 - valid part number combinations www .a lsc.com alliance semiconductor 11 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1002 packag e options dev i ce master des c ription fpbg a-1 00 (1mm pitch) lqfp -100 as91l10 01 jtag te st controlle r x x as91l10 02 jtag te st seque ncer x x as91l10 03 u 3 - p o r t g a t e w a y x x as91l10 06b u 6 - p o r t g a t e w a y x x table 7 - jt ag contr o ller produc t family www .a lsc.com alliance semiconductor 12 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.
july 2004 as91l1002 www .a lsc.com alliance semiconductor 13 200 3, 2 0 0 4 ? cop y right al lia nc e se mic o n duc tor cor p orati on. all ri ghts res e rv ed.

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